1. Field of the Invention
The present invention relates to a semiconductor device and a system using the same, and particularly, relates to a structure of an input/output interface of a semiconductor device for forming a high speed system. More particularly, the invention relates to a structure of an interface which does not cause ringing even if a signal level transition time is reduced.
2. Description of the Background Art
FIG. 21 schematically shows an example of a structure of a data processing system in the prior art. In FIG. 21, a processing unit (CPU) PC and a plurality of memory devices M1-Mn are commonly connected to a data bus DB. Processing unit (CPU) accesses memory devices M1-Mn via data bus DB. In recent years, the data transfer speed of memory devices M1-Mn has been increased in accordance with increase in internal operation speed of processing unit (CPU) PC.
FIG. 22 shows an example of a structure of a data output portion of one bit in memory devices M1-Mn. In FIG. 22, a data output circuit includes a logic determining portion 900 receiving an output enable signal OE and an internal data signal DATA, to determine a logic level of output data, a timing adjusting portion 902 for adjusting timing of the output signal of logic determining portion 900, and an output portion (driver) 904 for driving a transfer line 906 in accordance with the output signal of timing adjusting portion 902.
Logic determining portion 900 includes an inverter 900a inverting output enable signal OE, an NAND circuit 900b receiving output enable signal OE and internal data DATA, and an NOR circuit 900c receiving the output signal of inverter 900a and internal data DATA.
In a general memory system, as shown in FIG. 21, a plurality of memory devices M1-Mn are coupled to data bus DB. Therefore, output enable signal OE is used for preventing conflict between data on data bus DB (data transfer line 906). In this logic determining portion 900, when output enable signal OE is at L-level, the output signal of NAND circuit 900b is at H-level, and the output signal of NOR circuit 900c is at L-level so that transfer of internal data DATA is not performed. When output enable signal OE attains H-level, NAND circuit 900b and NOR circuit 900c operate as inverters, each of which inverts internal data DATA and applies the inverted data to timing adjusting portion 902 in the next stage.
Output driver 904 includes a P-channel MOS transistor (insulated gate field effect transistor) 904a and an N-channel MOS transistor 904b.
Timing adjusting portion 902 includes a first timing adjusting circuit 902a for adjusting the timing of the output signal of NAND circuit 900b, to apply a drive signal to a gate of P-channel MOS transistor 904a of output driver 904, and a second timing adjusting circuit 902b receiving the output signal of NOR circuit 900c, for adjusting timing thereof to apply the timing-adjusted signal to a gate of N-channel MOS transistor 904b of output driver 904. Timing adjusting portion 902 adjusts the timing of the signals applied from logic determining portion 900 for avoiding such a situation that both MOS transistors 904a and 904b of output driver 904 are simultaneously turned on to cause flow of a through-current. More specifically, first timing adjusting circuit 902a adjusts a waveform of its output signal such that the rising of the output signal may be sharp for achieving faster turn-off of MOS transistor 904a of output driver 904, while the falling of the output signal may be slowed. Second timing adjusting circuit 902b likewise adjusts the timing so as to make the falling of its output signal sharp for achieving faster turn-off of MOS transistor 904b of output driver 904, and to slow down the rising of the output signal. Thereby, the MOS transistors in output driver 904 to be turned off rapidly attain the off state, and paths of a through-current are rapidly cut off for preventing occurrence of the through-current.
When output enable signal OE is at L-level, the output signal of NAND circuit 900b is at H-level, and the output signal of NOR circuit 900c is at L-level. In output driver 904, both MOS transistors 904a and 904b are off, and the output circuit is at an output high impedance state. Thus, this data output circuit is a tristate output circuit.
FIG. 23 shows an example of a structure of an input portion for one-bit data. In FIG. 23, the input circuit includes an NOR circuit 910 which receives write data sent through transfer line 906 and a chip select signal CS, and an inverter 912 which inverts and transmits the output signal of NOR circuit 910 to an internal circuit. Chip select signal CS designates that the memory device is selected and has to be received write data. By applying chip select signal CS to NOR circuit 910, it is determined whether the input signal is to be activated or not. Further, the level for determining the logic level applied through transfer line 906 is adjusted by adjusting the input logic threshold voltage. Inverter 912 in the next stage adjusts delay of rising and falling of the write data applied from NOR circuit 910. NOR circuit 910 is formed of MOS transistors, which receive on their respective gates the signal sent through transfer line 906 and chip select signal CS. The gate of each MOS transistor is electrically isolated from other internal nodes by a gate insulating film. Therefore, transfer line 906 is not electrically terminated, and is electrically floated.
In the data processing system, memory devices are arranged on a board, and are connected together via on-board interconnection lines. Data bus DB shown in FIG. 21 is on-board interconnection lines, and other control signals, a clock signal or the like are transmitted via on-board interconnection lines. The on-board interconnection line is greater in line width than internal interconnection lines of the memory devices, and has a relatively large parasitic impedance and a relatively large parasitic capacitance (e.g., parasitic capacitance with respect to the board).
FIG. 24 schematically shows a distribution of parasitic impedances on the transfer line. In FIG. 24, the transfer line has a parasitic resistance Ru per unit length, an inductance Lu per unit length and a parasitic capacitance Cu per unit length. Parasitic resistance Ru and inductance Lu are connected in series. Parasitic capacitance Cu is connected between the transfer line and a ground node (board). In the case where the impedances are distributed on the transfer line as described above, a characteristic impedance Z can be represented by the following formula, assuming that resistance value R can be neglected. EQU Z=(Lu.multidot.Cu)
A propagation delay time tpdu per unit length of the transfer line having the characteristic impedance Z is expressed by the following formula: EQU tpdu=(Lu.multidot.Cu)
The output circuit shown in FIG. 22 must perform fast transfer of data via the transfer line having characteristic impedance Z. By increasing the size (ratio of gate width to gate length) of MOS transistors 904a and 904b included in output driver 904 shown in FIG. 22, or by reducing the equivalent resistances (channel resistances in the on-state) of the MOS transistors, the level transition time of the transfer signal becomes short, and the data transfer speed can be increased. However, if such fast data transfer is performed, the parasitic inductance and parasitic capacitance of the transfer line would cause signal reflection on the end, i.e., on the data input side to cause ringing if the equivalent resistances of MOS transistors 904a and 904b of the output driver are not matched with the impedance of the transfer line.
FIG. 25 shows a reflection coefficient and transmission coefficient of the transfer line. In FIG. 25, a transfer line 920 having a characteristic impedance Z1 is connected to a transfer line 922 having a characteristic impedance Z2. FIG. 25 shows a case where a signal is transferred from transfer line 920 to transfer line 922. A reflection coefficient .GAMMA. between transfer lines 920 and 922 can be expressed by the following formula: EQU .GAMMA.=(Z2-Z1)/(Z2+Z1)
The transmission coefficient is given by (1+.GAMMA.). The signal having an amplitude equal to a product of the signal amplitude and the reflection coefficient .GAMMA. is reflected on a boundary between transfer lines 920 and 922. If the reflection coefficient .GAMMA. is positive, reflection occurs in the same phase. If the reflection coefficient .GAMMA. is negative, reflection occurs in the opposite phase.
Description will now be given on the case shown in FIG. 26. As shown in FIG. 26, the signal sent from output driver 904 shown in FIG. 22 is transferred via a transfer line 924 with characteristic impedance Z of 50.OMEGA. and a whole signal propagation delay time Td of 3 ns. Each of MOS transistors 904a and 904b included in output driver 904 has an equivalent resistance (channel resistance in the on-state) of R. Transfer line 924 is connected to a gate of a MOS transistor 926 on an initial input stage on the signal receiving side. Input MOS transistor 926 has an infinite input impedance. A reflection coefficient .GAMMA.A on output stage TA is expressed by the following formula: EQU .GAMMA.A=(R-Z)/(R+Z)
A reflection coefficient .GAMMA.B on a signal receiving end TB of transfer line 924 is expressed by the following formula: EQU .GAMMA.B=(.infin.-Z)/(.infin.+Z)=1
FIGS. 27 and 28 show signal waveforms on sending end TA and receiving end TB of the signal transfer line shown in FIG. 26, respectively. FIG. 27 shows the signal waveforms on signal sending end TA and signal receiving end TB under the conditions of R&lt;Z. In the signal output operation, the potential on signal sending end TA attains the level determined by resistance division by equivalent resistance R of MOS transistor 904a and characteristic impedance Z of transfer line 924. This potential on the sending end TA is transferred onto transfer line 924, and reaches data receiving end TB upon elapsing of propagation time Td. On data receiving end TB, reflection occurs with reflection coefficient .GAMMA.B of 1, and the signal amplitude is doubled. The reflected wave reaches data sending end TA upon elapsing of propagation time Td, and reflection occurs with reflection coefficient of .GAMMA.A. The amplitude of this reflected wave decreases (reflection in the opposite phase). This reflected wave reaches signal receiving end TB again upon elapsing of propagation time Td. The width of lowering is doubled by the total reflection signal, and the signal is transferred to signal sending end TA again. Thereafter, the above operations are repeated.
Accordingly, if characteristic impedance Z is larger than equivalent resistance R of MOS transistor 904a, ringing occurs on signal receiving end TB. When this ringing changes exceeding a minimum level VIHmin for determining the H-level, the logic level of the signal cannot be accurately determined on the signal receiving side, and the determination of the input signal logic level must be delayed until the ringing is settled. Similar ringing occurs at the time of rising of the signal.
Accordingly, large ringing occurs on the side of the receiving end if output MOS transistors 904a and 904b in output driver 904 have reduced equivalent resistances R for driving transfer line 924 with a large current driving capability. When MOS transistor 904b in output driver 904 is turned on, ringing likewise occurs due to undershoot which in turn lowers beyond the ground voltage level.
FIG. 28 shows signal waveforms on signal transmission end TA and signal receiving end TB in the case where equivalent resistances R of output MOS transistors 904a and 904b of output driver 904 are greater than characteristic impedance Z of signal transfer line 927. A relationship between the signal sending and receiving systems is the same as that shown in FIG. 26. As shown in FIG. 28, if equivalent resistance R is greater than characteristic impedance Z, a signal at the potential level determined by resistance division by equivalent resistance R and characteristic impedance Z is generated on signal sending end TA. The potential at the end TA is transmitted to signal receiving end TB, and is reflected with reflection coefficient .GAMMA.B of 1, so that the signal amplitude is doubled. This reflected amplitude is transmitted to signal sending end TA again upon elapsing of time Td, and is reflected again with reflection coefficient .GAMMA.A. Since reflection coefficient .GAMMA.A is positive, reflection in the same phase occurs so that the signal voltage level rises on signal sending end TA. Thereafter, the reflection is repeated so that the signal voltage level gradually rises on signal receiving end TB. In the case shown in FIG. 28, ringing does not occur, and the voltage level of the input signal on signal receiving end TB gradually rises. However, equivalent resistance R is large and the current drive capability of output driver 904a is small (size is small), resulting in a problem that fast driving of transfer line 924 and therefore fast signal transfer are impossible.
As described above, if equivalent resistances R of MOS transistors 904a and 904b included in output driver 904 are increased for preventing occurrence of ringing, the signal level transition time increases so that it is impossible to increase the signal transfer rate via transfer line 906, and a high speed processing system cannot be achieved.
For preventing ringing on data receiving end TB of the transfer line, equivalent resistance R should be matched with characteristic impedance Z of transfer line 924 (R=Z), to set reflection coefficient .GAMMA.A on data sending end TB of the transfer line to 0 and to set reflection coefficient .GAMMA.B on data receiving end TB of the transfer line to 1. However, if such impedance matching is achieved, equivalent resistances R of output MOS transistors 904a and 904b increase, and the current drive capabilities of MOS transistors 904a and 904b decrease so that it is impossible to send a signal with steep rising and falling. Accordingly, it is necessary to send and receive a signal which rises and falls slowly, as shown in FIG. 29. Therefore, it is necessary to delay the logic determination of the input signal for time td, so that fast transfer of data/signal cannot be achieved. Thus, the level transition time of the data/signal is long so that the signal/data transfer rate on the transfer line cannot be increased.
For overcoming the above problems, several kinds of fast input/output interfaces have been proposed. However, they have not yet overcome the problems fundamentally.
FIG. 30A schematically shows a structure of a fast I/O (input/output) interface in the prior art. In FIG. 30A, a device 930 on a sending side and a device 940 on a receiving side are coupled via transfer lines 932 and 934 transferring complementary signals. The signals transferred through transfer lines 932 and 934 change between a power supply voltage VCC and a ground voltage GND.
Sending device 930 includes an output logic converter 930a for converting a logic level of a signal applied from an internal circuit to produce complementary signals, an output drive circuit 930b for driving transfer line 932 in accordance with the output signal of output logic converter 930a,and an output drive circuit 930c for driving transfer line 934 in accordance with the output signal of output logic converter 930a. Output drive circuits 930b and 930c transmit complementary signals onto transfer lines 932 and 934.
Receiving device 940 includes a differential sense circuit 940a for differentially amplifying the complementary signals transferred via transfer lines 932 and 934, to determine the logic level for generating a signal onto an internal circuit.
Complementary signals are transferred via transfer lines 932 and 934, and the complementary signals are differentially sensed by differential sense circuit 940a in receiving device 940, whereby signals of a small amplitude can be transmitted, and fast signal transfer can be rachieved.
Even in the structure of the above fast I/O interface, however, ringing occurs on the input portion of the receiving device if impedance matching is not achieved. Therefore, if the ringing occurs in the input stage of differential sense circuit 940a, and the logic levels of the complementary signals are inverted as shown in FIG. 30B, an error may occur in determination of the logic level of the input signal in differential sense circuit 940a, and an erroneous internal signal may be produced. Accordingly, in the fast I/O interface described above, the determination of the logic level must be performed after the ringing is sufficiently damped and a stable state is attained. Therefore, it is difficult to ensure fast I/O interface.
The foregoing problems related to the ringing arise not only in general memory systems and data processing systems but also in systems performing fast transfer of signals. In the memory devices, problems of ringing data may be caused by transfer of clock signals, control signal, address signals or the like, as in data transfer.